1. Field of the Invention
The present invention relates to electronic computers, and more particularly to computers which detect and handle a failure that may occur on a PCI express path.
2. Description of the Related Art
A typical computer system having a PCI express path includes a root port that functions as a PCI express bridge (hereinafter, PCI Express is abbreviated to “PCIe”). The root port is connected to a CPU through a primary bus, and is connected to a PCI express path through a secondary bus. The PCIe path forms a PCIe tree that includes a PCIe switch and a PCIe device which each are connected to the corresponding root port.
A failure which has occurred in the PCIe device is notified to the root port through downstream and upstream ports of the PCIe switch. The root port notifies the CPU of this failure by interrupting the CPU through the primary bus. A failure on another PCIe path including a PCIe switch is notified to the root port through a PCIe switch in which the failure has been detected, or through a higher level PCIe switch connected to the PCIe switch.
Incidentally, such techniques as described above are disclosed by JP-A-2004-348335 and JP-A-2005-196351 for example.